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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Clock Period Jitter
Cycle Time Derating for Core Timing Parameters
For a given number of clocks ( t n PARAM), when t CK(avg) and t ERR( t n PARAM),act exceed
t ERR( t n PARAM),allowed,
cycle time derating may be required for core timing parame-
CycleTimeDerating = max PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tCK(avg) , 0
ClockCycleDerating = RU PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tnPARAM
ters.
t t t t t
tnPARAM
Cycle time derating analysis should be conducted for each core timing parameter. The
amount of cycle time derating required is the maximum of the cycle time deratings de-
termined for each individual core timing parameter.
Clock Cycle Derating for Core Timing Parameters
For each core timing parameter and a given number of clocks ( t n PARAM), clock cycle
derating should be specified with t JIT(per).
For a given number of clocks ( t n PARAM), when t CK(avg) plus ( t ERR( t n PARAM),act) ex-
ceed the supported cumulative t ERR( t n PARAM),allowed, derating is required. If the
equation below results in a positive value for a core timing parameter ( t CORE), the re-
quired clock cycle derating will be that positive value (in clocks).
t t t t t
tCK(avg)
Cycle-time derating analysis should be conducted for each core timing parameter.
Clock Jitter Effects on Command/Address Timing Parameters
Command/address timing parameters ( t IS, t IH, t ISCKE, t IHCKE, t ISb, t IHb, t ISCKEb,
t IHCKEb) are measured from a command/address signal (CKE, CS, or CA[9:0]) transi-
tion edge to its respective clock signal (CK/CK#) crossing. The specification values are
not affected by the t JIT(per) applied, because the setup and hold times are relative to
the clock signal crossing that latches the command/address. Regardless of clock jitter
values, these values must be met.
Clock Jitter Effects on READ Timing Parameters
t RPRE
When the device is operated with input clock jitter, t RPRE must be derated by the
t JIT(per),act,max of the input clock that exceeds t JIT(per),allowed,max. Output derat-
ings are relative to the input clock:
tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max
tCK(avg)
For example, if the measured jitter into a LPDDR2-800 device has t CK(avg) = 2500ps,
t JIT(per),act,min
= –172ps, and t JIT(per),act,max = +193ps, then t RPRE,min,derated =
0.9 - ( t JIT(per),act,max - t JIT(per),allowed,max)/ t CK(avg) = 0.9 - (193 - 100)/2500 =
0.8628 t CK(avg).
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
139
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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